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| type package tle 4275 d v33 pg-to252-5-11 (rohs compliant) tle 4275 g v33 pg-to263-5-1 (rohs compliant) pg-to252-5-11 pg-to263-5-1 datasheet 1 rev. 1.1, 2015-01-15 linear voltage regulator 3.3 v fixed output voltage tle 4275 v33 feature overview ? output voltage 3.3 v 2 % ? current capability 400 ma ? stable with ceramic output capacitor ? reset circuit functional without supply voltage present ? reset output active low down to v q = 1 v ? reset circuit sensing the output voltage with programmable delay time ? maximum input voltage -42 v v i +45 v ? esd resistivity 4 kv (human body model) ? reverse polarity protection ? short circuit protection ? overtemperature shutdown ? automotive temperature range -40 c t j 150 c ? green product (rohs compliant) ? aec qualified the tle 4275 v33 is a monolithic integrated low dropout fixed output voltage regulator for loads up to 400ma. an integrated reset generator with adjustable power-on delay time as well as several protection circuits predestine th e ic for supplying microprocessor systems in an auto motive environment. figure 1 simplified block diag ram and typical application reset generator bandgap reference protection circuits gnd d q ro c q c d load e. g. micro controller gnd i supply regulated output voltage b lockdiagram_a ppc ircuit1.vsd tle 4275 v33 or: +5v
datasheet 2 rev. 1.1, 2015-01-15 tle 4275 v33 pin definitions and functions 1 pin definitions and functions figure 2 pin assignment pin symbol function 1i regulator input and ic supply. ? for compensating line influences, a capacit or to gnd close to the ic terminals is recommended. 2ro reset output. ? open collector output. external pull-up resistor to a positive voltage rail required. ? leave open if the reset function is not needed. 3gnd pg-to263-5-1 only: ground reference. ? connect to tab and heatsink area 4d reset delay timing. ? connect a ceramic capacitor to gnd for reset delay ti ming adjustment. ? leave open if the reset function is not needed. 5q regulator output . ? block to gnd with a capacitor close to the ic terminals, respecting capacitance and esr requirements given in the table ?functional range?. tab gnd pg-to252-5-11 only: ground reference. ? connect to heatsink area. tab ? pg-to263-5-1 only: ? connect to heatsink area and ground reference (pin 3). aep02580 15 ro dq gnd gnd ro iep02528 d q pg-to252-5-11 pg-to263-5-1 tle 4275 v33 electrical characteristics datasheet 3 rev. 1.1, 2015-01-15 2 electrical characteristics 2.1 absolute maximum ratings note: stresses above the ones listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection f unctions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?out side? normal operating range. protection functions are not designed for continuou s repetitive operation. -40 c t j 150 c; all voltages with respect to ground (unless otherwise specified) pos. parameter symbol limi t values unit conditions min. max. regulator input and ic supply i 2.1.1 voltage v i -42 45 v ? 2.1.2 current i i ??ma internally limited regulator output q 2.1.3 voltage v q -1 16 v ? 2.1.4 current i q ??ma internally limited reset output ro 2.1.5 voltage v ro -0.3 25 v ? 2.1.6 current i ro -5 5 ma reset delay timing d 2.1.7 voltage v d -0.3 7 v ? 2.1.8 current i d -2 2 ma ground gnd 2.1.9 current i gnd ??ma internally limited temperatures 2.1.10 junction temperature t j -40 150 c? 2.1.11 storage temperature t stg -50 150 c? esd susceptibility 2.1.12 esd resistivity v esd,hbm -4 4 kv hbm 1) 1) esd susceptibility, human body model ?hbm? according to eia/jesd 22-a114b. 2.1.13 v esd,cdm -500 500 v cdm 2) 2) esd susceptibility, charged device model ?cd m? according to eia/jesd22-c101 or esda stm5.3.1 moisture level 2.1.14 moisture level msl 1?? datasheet 4 rev. 1.1, 2015-01-15 tle 4275 v33 electrical characteristics 2.2 functional range note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 2.3 thermal resistance pos. parameter symbol limit values unit conditions / remarks min. max. 2.2.1 input voltage v i 4.4 42 v v q = v i - v dr 1) 1) for details on max. output current vs. input voltage see table 1: electri cal characteristics voltage regulator 2.2.2 junction temperature t j -40 150 c? 2.2.3 output capacitor c q 22 ? f ? 2) 2) the minimum output capacitance requ irement is applicable for a worst case capacitance tolerance of 30% 2.2.4 esr cq ?3 ? pos. parameter symbol typ. value unit conditions package p-to252-5: 2.3.1 junction ? ambient pg-to252-5-11 r th,j-a 144 k/w footprint only 1) 1) eia/jesd 52_2, fr4, 80 80 1.5 mm; 35 cu, 5 sn; horizontal position; zero airflow. not subject to production test; specified by design. 2.3.2 78 k/w 300 mm 2 pcb heatsink area 1) 2.3.3 55 k/w 600 mm 2 pcb heatsink area 1) 2.3.4 junction ? case pg-to252-5-11 r th,j-c 1.8 k/w package p-to263-5: 2.3.1 junction ? ambient pg-to263-5-1 r th,j-a 79 k/w footprint only 1) 2.3.2 53 k/w 300 mm 2 pcb heatsink area 1) 2.3.3 39 k/w 600 mm 2 pcb heatsink area 1) 2.3.4 junction ? case pg-to263-5-1 r th,j-c 1.3 k/w tle 4275 v33 block description and electrical characteristics datasheet 5 rev. 1.1, 2015-01-15 3 block description and electrical characteristics 3.1 voltage regulator the output voltage v q is controlled by comparing a portion of it to an internal reference and driving a pnp pass transistor accordingly. the control loop stability depends on th e output capacitor c q , the load current, the chip temperature and the poles/zeros introduced by the integr ated circuit. to ensure st able operation, the output capacitor?s capacitance and its equivalent series resist or esr requirements given in the table ?operating range? have to be maintained. for details see also the typica l performance graph ?output capacitor series resistor esr cq vs. output current i q ?. also, the output capacitor shall be sized to buffer load transients. an input capacitor c i is strongly recommended to buffer line influe nces. connect the capaci tors close to the ic terminals. protection circuitry prevent the ic as well as the application from destruction in case of catastrophic events. these safeguards contain output current limit ation, reverse polarity protection as well as thermal shutdown in case of overtemperature. in order to avoid excessive power dissipation that could never be handled by the pass element and the package, the maximum output current is decreased at input voltages above v i =22v. the thermal shutdown circuit prevents the ic from i mmediate destruction under fa ult conditions (e.g. output continuously short-circuited) by switching off the powe r stage. after the chip has cooled down, the regulator restarts. this leads to an oscillatory behaviour of the output vo ltage until the fault is re moved. however, junction temperatures above 150 c are outside the maximum rating s and therefore significantly reduce the ic lifetime. the tle 4275 v33 allows a negative supply voltage. however, several sma ll currents are flowing into the ic increasing its junction temperature. th is has to be considered for the therma l design, respecting that the thermal protection circuit is not operating during reverse polari ty conditions for details see typical performance graphs. figure 3 block diagram voltage regulator circuit bandgap reference gnd q i blockdiagram_voltageregulator.vsd satur ation contr ol cur rent limitation temperature shutdown c q esr c } load supply c i regulated output voltage datasheet 6 rev. 1.1, 2015-01-15 tle 4275 v33 block description and electrical characteristics 3.2 current consumption table 1 electrical characteristics voltage regulator v i = 13.5 v; -40 c t j 150 c (unless otherwise specified) pos. parameter symbol limit values unit remark / test condition min. typ. max. 3.1.1 output voltage v q 3.23 3.3 3.37 v 1 ma i q 400 ma; 5 v v i 28 v 3.1.1 3.23 3.3 3.37 v 1 ma i q 300 ma; 4.4 v v i 28 v 3.1.2 3.23 3.3 3.37 v 1 ma i q 200 ma; 4.4 v v i 40 v 3.1.3 load regulation steady-state d v q,load -30 -15 ? mv i q = 5 ma to 400 ma; v i = 6 v 3.1.4 line regulation steady-state d v q,line ?5 15mv v i = 8 v to 32 v; i q = 5 ma 3.1.5 power supply ripple rejection psrr ?60? db f ripple = 100 hz; v ripple = 0.5 vpp 1) 1) parameter not subject to produ ction test; specified by design. 3.1.6 output current limitation i q,max 401 ? 1000 ma v q = 3.0 v 3.1.7 overtemperature shutdown threshold t j,sd 151 ? 200 c t j increasing 1) 3.1.8 overtemperature shutdown threshold hysteresis t j,hy ?25? k table 2 electrical characteristics current consumption v i = 13.5 v; -40 c t j 150 c (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 3.2.1 current consumption i q = i q - i i i q ? 180 220 a i q = 1 ma; t j = 25 c 3.2.2 ? 180 240 a i q = 1 ma; t j 85 c 3.2.3 ? 8 12 ma i q = 250 ma 3.2.4 ? 20 30 ma i q = 400 ma tle 4275 v33 block description and electrical characteristics datasheet 7 rev. 1.1, 2015-01-15 3.3 reset function the reset function cont ains serveal features: output undervoltage reset: an output undervoltage condition is indicated setting t he reset output ?ro? to low. this signal might be used to reset a microcontroller during low supply voltage. in case the battery voltage is alread y lower than the buffered output voltage v q of the voltage regulator, the reset circuit is supplied from the outp ut ?q?, ensuring a defined rese t switching threshold also at v i = 0 v. the reset output ?ro? is held ?low? down to an output voltage of v q = 1 v, even if the input voltage v i is 0 v. power-on reset delay time: the power-on reset delay time t d,pwr-on allows a microcontoller and oscillator to start up. this delay time is the time period from exceeding the reset switching threshold v rt until the reset is released by switching the reset output ?ro? from ?low? to ?high?. the power-on reset delay time t d,pwr-on is defined by an external delay capacitor c d connected to pin ?d? which is charged up by the delay capacitor charge current i d,ch starting from v d = 0 v. for easy calculating the power-on re set delay time, a multiplier factor f d,pwr-on = t d,pwr-on / c d is specified. hence, t d,pwr-on becomes: t d,pwr-on = f d,pwr-on / c d . (1) for a precise calculation consider also the delay capacitor?s tolerance. undervoltage reset delay time: unlike the power-on reset delay time, the undervoltage reset delay t d time considers a short output undervoltage event where the delay capacitor c d is assumed to be discharged to v d = v dst,lo only before the charging sequence restarts. therefore, the undervoltage reset delay time t d is defined by the delay capacitor charge current i d,ch starting from v d = v dst,lo and the external delay capacitor c d . for easy calculating the undervoltage re set delay time, a multiplier factor f d = t d / c d is specified. hence, t d becomes: t d = f d / c d . (2) for a precise calculation consider also the delay capacitor?s tolerance. reset reaction time: the total reset reaction rime t rr,total considers the internal reaction time t rr,int and the discharge time t rr,d defined by the external delay capacitor c d (see typical performance graph for details ). hence, the total reset reaction rime becomes: t rr,total = t rr,int + t rr,d . (3) reset output ?ro? low for v q 1v: in case of an undervoltage reset condition reset output ?ro? is held ?low? for v q 1 v, even if the input voltage v i is 0 v. this is achieved by supplying th e reset circuit from the output capacitor. datasheet 8 rev. 1.1, 2015-01-15 tle 4275 v33 block description and electrical characteristics reset output ?ro?: the reset output ?ro? is an open collector output requ iring an external pull-up resistor to a voltage rail v io . as the maximum reset output sink current i ro,max is limited, the minimum external pull-up resistor calculates: r ro,external,min = v io / i ro,max . (4) figure 4 block diagram reset circuit figure 5 timing diagram reset gnd q i blockdiagram_resetstandard_ro nopullup.vsd supply ro v dst int. supply i d,ch i dr,dsch v rt control d c d reset c q vdd micro- controller gnd or e.g. +5 v aed03010 thermal t rd power-on-reset voltage dip secondary overload at output spike v d,c = v d dt v q q, rt v t rr < rr t at input undervoltage shutdown c d t v ro d v t t t v du v drl tle 4275 v33 block description and electrical characteristics datasheet 9 rev. 1.1, 2015-01-15 table 3 electrical characteristics reset function v i = 13.5 v; -40 c t j 150 c (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. pos. parameter symbol limit values unit conditions / remarks min. typ. max. output undervoltage reset comperator: 3.3.1 output undervoltage reset switching threshold v rt1 3.06 3.13 3.2 v v i 4.4 v v q decreasing 3.3.2 v rt2 2.5 2.9 v rt1 v v i = 0 v v q decreasing 3.3.3 output undervoltage reset headroom v rh 100 130 ? mv calculated value: v q,nom - v rt . v i 4.4 v reset output ro: 3.3.4 reset output low voltage v ro,low ? 0.2 0.4 v 1 v v q v rt ; i ro = 0.3 ma 3.3.5 reset output sink current limitation i ro,max 0.3 ? ? ma 1 v v q < v rt ; v ro = 3.3v 3.3.6 reset output external pull-up resistor to v q r ro 3.3 ? ? k v ro 0.4 v at reset condition 3.3.7 reset output leakage current i ro,leak ?02a v ro = 5 v reset delay timing: 3.3.8 upper delay switching threshold v dst,hi ?1.8?v? 3.3.9 lower delay switching threshold v dst,lo ?0.6?v? 3.3.10 delay capacitor charge current i d,ch ?6?a v d = 1 v 3.3.11 delay capacitor reset discharge current i dr,dsch ? 70 ? ma v d = 1 v 3.3.12 undervoltage reset delay time factor f d = t d / c d f d 0.13 0.20 0.27 ms / nf calculated value: f d = ( v dst,hi - v dst,lo ) / i d,ch c d 10 nf 1) 1) for lower values of c d , the accuracy given is not guaranteed; see typ. performance graph for details. 3.3.13 power-on reset delay time factor f d,pwr-on = t d,pwr-on / c d f d,pwr-on 0.21 0.30 0.39 ms / nf calculated value: f d = c d * v dst,hi / i d,ch c d 10 nf 1) 3.3.14 delay capacitor discharge time t rr,d ?0.72scalculated value: t rr,d = c d *( v dst,hi - v dst,lo )/ i d,dsch c d = 47 nf 3.3.15 internal reset reaction time t rr,int ?26.5s c d = 0 nf 2) 2) parameter not subject to production test; specified by design. datasheet 10 rev. 1.1, 2015-01-15 tle 4275 v33 package outlines 4 package outlines figure 6 pg-to252-5-11 package outline and footprint figure 7 pg-to263-5-1 package outline and footprint green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb- free finish on leads and suitable for pb-fre e soldering according to ipc/jedec j-std-020). find more package info rmation on the infineon internet pa ge: http://www.infineon.com/packages. 1) includes mold flashes on each side. 4.56 0.25 m a 6.5 5.7 max. ?.1 per side 0.15 max. -0.2 6.22 ?.5 9.98 (4.24) 1 a 1.14 5 x 0.6 ?.15 0.8 ?.1 +0.15 -0.05 0.1 b -0.04 +0.08 0...0.15 0.51 min. 0.5 b 2.3 -0.10 0.5 +0.05 -0.04 +0.08 (5) -0.01 0.9 +0.20 b 1) all metal surfaces tin plated, except area of cut. 5.36 5.8 10.6 6.4 0.34 0.8 2.2 tle 4275 v33 revision history datasheet 11 rev. 1.1, 2015-01-15 5 revision history revision date changes 1.1 2015-01-15 parameter 2.1.14 msl min. value changed from 3 to 1. 1.0 2006-09-22 edition 2015-01-15 published by infineon technologies ag, 81726 munich, germany ? infineon technologies ag 2006. all rights reserved. attention please! the information given in this data sheet shall in no event be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the app lication of the device, infi neon technologies hereby disclaims any and all warran ties and liabilities of any kind, includin g without limitation warranties of non- infringement of intellectual property rights of any third party. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. |
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